The present invention relates to a microcomputer and also to electronic equipment and a debugging system comprising the same.
There has recently been increasing demand for the incorporation of microcomputers that are capable of implementing high-level information processing into electronic equipment such as game machines, car navigation systems, printers, and portable information terminals. Such a thus-incorporated microcomputer is usually mounted on a user board called a target system. A software development support tool called an in-circuit emulator (ICE) is widely used for supporting the development of software to be used in the target system.
The CPU-switching type of ICE shown in FIG. 1 is the most common type of this kind of ICE used in the art. With this CPU-switching ICE, a microcomputer 302 is removed from a target system 300 during debugging, and a probe 306 of a debugging tool 304 is connected thereto instead. This debugging tool 304 emulates the operation of the removed microcomputer 302. The debugging tool 304 can also perform various processes necessary for debugging.
However, if the internal operating frequency of the microcomputer 302 of the CPU-switching ICE rises, it becomes difficult to obtain a real-time trace, due to delays in the signals generated by the probe 306 and the buffer that stores trace information.
In addition, if an attempt is made to store trace information in a trace buffer without limitations, the trace buffer would soon overflow so that it may not be possible to acquire trace information for the portions necessary for debugging. In such a case, it would be immensely convenient a trace range can be specified for collecting trace information therein. However, if the internal operating frequency of the CPU were to rise, it would become difficult to implement a trace range specification with external circuitry such as that of a CPU-switching ICE.
Systems are being developed to enable real-time tracing on a mass-produced chip, thus solving the above problems. In such a case, it is necessary to have a dozen or so dedicated terminals for transferring information over the address bus as trace information and storing it in real-time into a trace buffer. These terminals are necessary only during debugging, however, so they are useless as far as the end user is concerned and thus it is preferable to reduce them as far as possible.
In addition, it would also be extremely convenient to have a function that is capable of accurately acquiring trace information within a specified range, even during the implementation of a real-time trace on a mass-produced chip.
The present invention was devised in the light of the above described technical problems with the objective of providing a microcomputer that makes it possible to implement a real-time trace on a mass-produced chip using few terminals, acquire trace information and measure execution times from within a specified range, together with electronic equipment and a debugging system comprising this microcomputer.
In order to solve the above problems, the present invention relates to a microcomputer having a real-time trace function, the microcomputer comprising a central processing unit for executing an instruction; instruction address setting means for setting an instruction address for detecting an execution of a plurality of instructions to be executed by the central processing unit; and detection signal output means for outputting a detection signal through a single detection signal output terminal, when the execution of the plurality of instructions has been detected.
In this aspect of the invention, it is possible to acquire information indicating that a plurality of instructions have been executed, using a single terminal. It is therefore possible to detect the occurrence of the execution of a plurality of instructions without substantially reducing the number of terminals that can be utilized by the user, which enables an increase in debugging efficiency.
In a further aspect of the present invention, the plurality of instructions comprises a first instruction and a second instruction, and the detection signal output means omits outputting a detection signal when the first instruction is successively executed after the first instruction is executed and a detection signal is output, and outputs a detection signal only when the second instruction is executed.
When a single terminal is used for acquiring execution information on a plurality of instructions, it is difficult to determine from the outside which instructions have been executed.
However, this aspect of the invention ensures that the detection signal is not output when the first and second instructions are executed in a sequence that differs from the expected sequence. Thus the detection signal is always output to the exterior to show that the first and second instructions are executed in the expected sequence.
This aspect of the invention therefore makes it possible to use a single terminal to acquire identifiable information concerning which instructions have been executed, even if a plurality of instructions have been executed in a sequence that differs from the expected sequence.
Another aspect of the present invention further comprises status information output means for outputting status information indicating an execution state of the central processing unit to a status information output terminals, wherein one of the status information output terminals is also used as the detection signal output terminal.
In this case, the status information is information necessary when performing a real-time trace, by way of example.
Since this aspect of the invention ensures that it is not necessary to provide another detection signal output terminal in addition to the status information output terminal, the number of debugging terminals can be further reduced.
In a yet further aspect of the present invention, the status information comprises information for identifying to which of the following states the execution state of the central processing unit belongs: ordinary instruction execution, relative branch instruction execution, absolute branch instruction execution, a match with the instruction address during ordinary instruction execution, a match with the instruction address during relative branch instruction execution, and a match with the instruction address during absolute branch instruction execution.
In this case, a PC relative branch instruction is an instruction to branch at an address that is explicitly written in the program, so it is possible to determine the branch destination from the source code. A PC absolute branch instruction is an instruction to branch at an address that is set by a value in a register during the execution of the program, so it is not possible to determine the branch destination from the source code.
This aspect of the invention enables to represent the execution state and the matching state with the instruction address of the central processing unit and the match state with the instruction address by only 6 types: ordinary instruction execution, relative branch instruction execution, absolute branch instruction execution, a match with the instruction address during ordinary instruction execution, a match with the instruction address during relative branch instruction execution, and a match with the instruction address during absolute branch instruction execution. This makes it possible to reduce the number of debugging terminals provided for the microcomputer to only three terminals.
In a still further aspect of the present invention, an instruction address that is set by the instruction address setting means comprises an address for specifying at least one of start and end of a trace range.
With this aspect of the invention, information for detecting the start or end of a trace range can be output from a single terminal. This makes it possible to provide a microcomputer that can implement a real-time trace on a mass-produced chip and acquire trace information from within a specified range, using only a few terminals.
In an even further aspect of the present invention, an instruction address that is set by the instruction address setting means comprises an address for specifying at least one of a start and end of a execution-time measurement range of a program.
This aspect of the invention makes it possible to output information for detecting the start and end of an execution-time measurement range, from a single terminal. This makes it possible to provide a microcomputer that can acquire information for determining the timing of the start and stop of execution-time measurement within a specified range, using only a few terminals.
In yet another aspect of the present invention, the instruction address setting means comprises a plurality of registers for holding instruction address information for detecting the execution of a plurality of instructions, and the detection signal output means comprises: means for holding a comparison result between an instruction address that was read out previously for instruction execution by the central processing unit and an address that has been held in each of the registers, until the instruction at the previously read-out instruction address is executed, and outputting a detection signal based on the held comparison result when the instruction at the previously read-out instruction address has been executed; and means for invalidating the comparison result with instructions that were read out before the branch instruction was executed when the executed instruction was a branch instruction.
In this case, the invalidation of the comparison result includes both initializing the storage area and resetting write and read pointers.
The present invention bases the detection of the execution of a plurality of instructions on previously read-out instructions, with the output of a detection signal indicating actual execution. This configuration enables optimal detection, even with a microcomputer that performs pipeline processing.
In still another aspect of the present invention, the registers comprise at least two registers for holding a start address and an end address for defining a given range of a program, and the detection signal output means comprises: first comparison means and second comparison means for comparing an instruction address, that was read out previously for instruction execution by the central processing unit, with the start address and the end address; a comparison result holding section that is capable of holding a plurality of comparison results from the first comparison means and the second comparison means; means for reading the comparison results held in the comparison result holding section, at a timing that the previously-read instruction has been executed; means for resetting any the comparison results held in the comparison result holding section when an executed instruction was a branch instruction; and a logic circuit for outputting a detection signal based on the comparison results that have been read from the comparison result holding section, when addresses that are held in the first register and the second register have been executed in a predetermined sequence.
During pipeline processing, there is a time lag between instruction acquisition and execution, making it difficult to acquire execution address information from the signal lines. This aspect of the invention makes it possible to acquire the comparison result obtained at the stage at which an instruction was previously read out for instruction execution, at the execution stage. This enables signal processing that can cope with pipeline processing.
Note that when a branch instruction has been executed, and even if the previously read-out instruction is not executed because of the generation of the branch instruction, the accurate determination is possible by resetting comparison results, which were held in the comparison result holding section, with previously read-out instruction before the branch instruction occurred.
Electronic equipment relating to another aspect of the present invention comprises any one of the above described microcomputers; an input source of data that is to be processed by the microcomputer; and an output device for outputting data that has been processed by the microcomputer.
This enables a shortening of the development period and a reduction in the cost of electronic equipment, due to more efficient debugging of programs running on that electronic equipment.
A further aspect of the present invention relates to a debugging system for a target system that comprises a microcomputer, wherein the microcomputer comprises: a central processing unit for executing an instruction; instruction address setting means for setting an instruction address for detecting an execution of a plurality of instructions to be executed by the central processing unit; and detection signal output means for outputting a detection signal through a single detection signal output terminal when the execution of the plurality of instructions has been detected, and the debugging system further comprises trace information acquisition means for receiving the detection signal from the microcomputer, and acquiring trace information by controlling a start and end of the acquisition of trace information based on the detection signal.
This aspect of the invention makes it possible to provide a debugging system that is capable of acquiring debugging information within a specified range, with only a few terminals.
A still further aspect of the present invention relates to a debugging system for a target system that comprises a microcomputer, wherein the microcomputer comprises: a central processing unit for executing an instruction; instruction address setting means for setting an instruction address for detecting an execution of a plurality of instructions to be executed by the central processing unit; and detection signal output means for outputting a detection signal through a single detection signal output terminal when the execution of the plurality of instructions has been detected, and the debugging system further comprises execution-time measurement means for receiving the detection signal from the microcomputer, and measuring execution time by controlling a start and end of measurement of program execution time based on the detection signal.
This aspect of the invention makes it possible to provide a debugging system that is capable of acquiring execution times within a specified range, with only a few terminals.
In a debugging system in accordance with an even further aspect of the present invention, the plurality of instructions comprises a first instruction and a second instruction, and the detection signal output means omits outputting a detection signal when the first instruction is successively executed after the first instruction is executed and a detection signal is output, and outputs a detection signal only when the second instruction is executed.
This aspect of the invention makes it possible to provide a debugging system that can identify which instructions of debugging have been executed, even if a plurality of instructions are executed in a sequence that differs from the expected sequence, using a single terminal.